All-Digital DLL Architecture and Applications

An improved architecture for all digital Delay Locked Loop (ADDLL) had been developed and implemented for several applications and design methodologies. In most cases it can be based on standard cells only. Several techniques are used to minimize the jitter, achieving less than 40pS (peak) for 0.13μ technology. The frequency range is very wide, exceeding 500MHz. For 0.13μ core, the area is 0.01mm, and power is 2mW at 500MHz with no standby power. Scaling to smaller geometries reduces jitter, power and area. The core was fabricated and tested on several technologies. The ADDLL enables several applications, such as clock de-skewing, frequency multiplications, splitting the cycle into several phases, controlling slave delay blocks and balancing clock skew in multiple voltage domain chips.